- 1 - e06947 this ic is an esd sensitive device. special handling precautions are required. the actual esd test data will be available later. sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illu strating the operation of the devices. sony cannot as sume responsibility for any problems aris ing out of the use of these circuits. CXG1216UR high power dp4t switch with logic control description the CXG1216UR can be used in wireless communication systems, for example, dual-band and triple-band cdma handsets. this ic has on-chip logic for operation with 4 coms control inputs. the sony jphemt process is used for low insertion loss and on-chip logic circuit. (applications: antenna switch for cellular handsets, dual-band and triple-band cdma) features ? low insertion loss: 0.35db@900mhz, 0.50db@2ghz ? 4 cmos compatible control line package small package size: 20-pin uqfn structure gaas jphemt mmic absolute maximum ratings (ta = 25 c) ? input power max. (rf port) pin 34 dbm ? bias voltage v dd 7v ? control voltage vctl 5 v ? operating temperature topr ?35 to +85 c ? storage temperature tstg ?65 to +150 c
CXG1216UR - 2 - block diagram and re commended circuit when using this ic, the following external components should be used: c rf : this capacitor is used for rf decoupling and must be used for all applications. cbypass: this capacitor is used for dc line filtering. f12 f11 f14 f13 f9 f10 f2 f3 f7 f4 f8 f1 f5 f6 7 6 14 rf3 (2ghz) 13 gnd 15 gnd 11 gnd ctlb ctld ctla rf1 (800mhz (1)) gnd 4 rf5 (ant) 2 gnd 1 rf6 (ext) c rf 5 gnd c rf rf2 (800mhz (2)) c rf 12 c rf rf4 c rf 10 20 8 ctlc 9 3 gnd gnd c rf gnd cbypass (100pf) v dd 19 17 18 16
CXG1216UR - 3 - truth table dc bias conditions (ta = 25 c) pin description state ctla ctlb ctlc ctld on state f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 1l lhl rf5 ? 1 (800mhz(1)-ant) on off off off off off off off off on on on off on 2l lhh rf5 ? 2 (800mhz(2)-ant) off on off off off off off off on off on on off on 3lhhl rf5 ? 3 (2ghz-ant) off off on off off off off off on on off on off on 4h l h l rf5 ? 4 (rf4-ant) off off off on off off off off on on on off off on 5llll rf6 ? 1 (800mhz(1)-ext) off off off off on off off off off on on on on off 6lllh rf6 ? 2 (800mhz(2)-ext) off off off off off on off off on off on on on off 7lhl l rf6 ? 3 (2ghz-ext) off off off off off off on off on on off on on off 8hlll rf6 ? 4 (rf4-ext) off off off off off off off on on on on off on off item min. typ. max. unit vctl (h) 1.5 2.6 3.2 v vctl (l) 0 ? 0.5 v v dd 2.62.853.2v pin no. symbol pin no. symbol 1rf6 (ext) 11gnd 2 gnd 12 rf4 3gnd 13gnd 4 rf5 (ant) 14 rf3 (2ghz) 5gnd 15gnd 6v dd 16 rf2 (800mhz (2)) 7ctla 17gnd 8 ctlb 18 rf1 (800mhz (1)) 9ctlc 19gnd 10 ctld 20 gnd
CXG1216UR - 4 - electrical characteristics (ta = 25 c, v dd = 2.85v) *1 pin = 25dbm, 0/2.6v control, v dd = 2.85v, 890 to 930mhz *2 pin = 25dbm, 0/2.6v control, v dd = 2.85v, 1.92 to 1.98ghz *3 pin = 25dbm (900mhz) + 25dbm (901mhz), 0/2.6v control, v dd = 2.85v *4 pin = 25dbm (1.9ghz) + 25dbm (1.901ghz), 0/2.6v control, v dd = 2.85v item symbol condition min. typ. max. unit insertion loss il 830 to 930mhz 0.35 0.55 db 1575.42mhz 0.40 0.60 db 1.92 to 2.17ghz 0.50 0.70 db isolation iso 830 to 930mhz 25 32 db 1575.42mhz 23 30 db 1.92 to 2.17ghz 20 30 db vswr vswr 50 1.2 ? switching speed tsw 5 10 s 1db compression input power p1db v dd = 2.85v 32 dbm harmonics 2fo *1 ?70 ?65 dbc 3fo *1 ?70 ?65 dbc 2fo *2 ?65 ?60 dbc 3fo *2 ?65 ?60 dbc input ip3 iip3 *3 55 60 dbm *4 55 60 dbm bias current idd v dd = 2.85v 200 250 a control current ictl vctl (h) = 2.6v to 1.5v 0 a vctl (l) = 0v ?8 ?5 ?3 a
CXG1216UR - 5 - sony corporation package outline (unit: mm) pin 1 index c 0.1 s a-b 0.4 0.05 m s c c a-b s 0.05 s max0.02 + 0.09 20pin uqfn (plastic) 0.25 ? 0.03 + 0.09 0.14 ? 0.03 x 4 2.7 1 5 11 15 16 20 6 10 2.7 s 0.4 0.1 1.3 0.55 0.05 4-r0.3 0.26 a b 0.25 0.14 0.07 0.18 sony code eiaj code jedec code package material lead treatment lead material epoxy resin solder plating copper alloy 0.02g package structure uqfn-20p-01 package mass terminal section note:cutting burr of lead are 0.05mm max. solder plating thermal die pad lead plating specifications item lead material copper alloy solder composition sn-bi bi:1-4wt% plating thickness 5-18m spec.
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